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tm
TE CH
T14L256A
SRAM
FEATURES
* High speed access time: 8/10/12/15ns(max.) * Low power consumption : Active 300 mW (typ.) * Single + 3.3 power supply * Fully static operation - No clock or refreshing required * All inputs and outputs directly LVTTL compatible * Common I/O capability * Available packages : 28-pin 300 mil, SOJ, TSOP-I (forward type) and lead-free package. * Output enable (OE ) available for very fast access
32K X 8 HIGH SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The T14L256A is a high speed, low power CMOS static RAM organized as 32,768 x 8 bits that operates on a single 3.3-volt power supply. This device is packaged in a standard 28-pin 300 mil SOJ or TSOP-I forward type and lead-free .
BLOCK DIAGRAM
Vcc VSS
A0 . . . A 14 CS OE WE CONTROL DATA I/O I/O 1 . . . I/O 8 DECODER CORE ARRAY
PIN CONFIGURATION
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
PIN DESCRIPTION
SYMBOL A0 - A14 I/O1 - I/O8
CS
SOJ
WE OE
Vcc Vss
28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PART NUMBER EXAMPLES
PACKAGE SPEED T14L256A-8J SOJ 8ns T14L256A-8JG SOJ/lead-free 8ns 8ns T14L256A-8P TSOP-I
TSOP-I
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 1
Publication Date: NOV. 2003 Revision: F
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T14L256A
DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage to Vss Potential Inputs to Vss Potential Power Dissipation Storage Temperature RATING -0.5 to + 4.6 -0.5 to Vcc +0.5 1.0 -60 to +150 UNIT V V W C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage Input Voltage, low Input Voltage, high Ambient Temperature SYM Vcc MIN Typ-5% -0.3 2.1 0 TYP 3.3 MAX Typ+5% 0.8 Vcc+0.3 70 UNIT V V V C
VIL VIH TA
TRUTH TABLE
CS H L L L OE X H L X WE X H H L MODE Not Selected Output Disable Read Write I/O1- I/O8 High-Z High-Z Data Out Data In Vcc
I SB, I SB1
Icc Icc Icc
OPERATING CHARACTERISTICS
(Vcc = 3.3V 5%, Vss = 0V, Ta = 0 to 70C)
PARAMETER Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current SYM. I LI I LO TEST CONDITIONS Vin=Vss to Vcc VI/O=Vss to Vcc , CS =VIH or
OE =
MIN. TYP. MAX. UNIT -10 +10 uA -10 +10 uA 2.4 0.4 110 100 90 80 15 2 V V mA mA mA mA mA mA
VIH or WE = VIL
VOL VOH
Icc
I OL = + 8.0mA I OH = - 4.0mA
8 10 Cycle = MIN. 12 Duty = 100% 15 CS=VIH , Cycle=MIN, Duty=100%
CS =VIL , I/O=0mA
I SB I SB1
CS Vcc -0.2V
Note: Typical characteristics are at Vcc = 3.3V, Ta = 25C
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 2
Publication Date: NOV. 2003 Revision: F
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T14L256A
CAPACITANCE
(Vcc = 3.3V, Ta = 25C, f = 1 MHz)
PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VOUT = 0V MAX. 6 8 UNIT pF pF
C IN C I/O
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0V to 3V 3 ns 1.5V C L =30pF,I OH /I OL = -4mA/8mA
AC TEST LOADS AND WAVEFORM
R1 320 ohm 3.3V OUTPUT 30pF Including Jig and Scope R2 350 ohm 5pF Including Jig and Scope R2 350 ohm R1 320 ohm
3.3V OUTPUT
(For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW )
3.0V 0V 3ns
90% 10% 10%
90%
3ns
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 3
Publication Date: NOV. 2003 Revision: F
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T14L256A
AC CHARACTERISTICS
(Vcc =3.3V 5%, Vss = 0V, Ta = 0 to 70C)
(1) READ CYCLE
PARAMETER Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYM.
T14L256A-8 T14L256A-10 T14L256A-12 T14L256A-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tRC tAA tACS tAOE tCLZ* tOLZ tCHZ* tOHZ tOH
8 3 0 2.5
8 8 5 4 4 -
10 3 0 3
10 10 6 5 5 -
12 3 0 3
12 12 7 6 6 -
15 3 0 0 0 3
15 15 7 7 7 -
ns ns ns ns ns ns ns ns ns
* These parameters are sampled but not 100% tested.
(2)WRITE CYCLE
PARAMETER Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write SYM.
T14L256A-8 T14L256A-10 T14L256A-12 T14L256A-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOHZ tOW
8 6 6 0 6 0 5 0 0
4 4 -
10 8 8 0 8 0 6 0 0
5 5 -
12 10 10 0 10 0 8 0 0
6 6 -
15 11 11 0 11 0 8 0 0
6 7 -
ns ns ns ns ns ns ns ns ns ns ns
* These parameters are sampled but not 100% tested.
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 4
Publication Date: NOV. 2003 Revision: F
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T14L256A
TIMING WAVEFORMS READ CYCLE 1
(Address Controlled)
tR C
A d d re s s
tA A tO H tO H
DOUT
READ CYCLE 2
(Chip Select Controlled)
CS
tA C S tC L Z tC H Z
DOUT
READ CYCLE 3
(Output Enable Controlled)
tR C
A d d re s s
tA A
OE
tA O E tO L Z tO H
CS
tA C S tC L Z tO H Z tC H Z
DOUT
DON' T CARE UNDEF INED
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 5
Publication Date: NOV. 2003 Revision: F
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Ad d r es s
TE CH
( OE CLOCK)
tW C
T14L256A
WRITE CYCLE 1
t
WR
OE
tC W
CS
t t AW WP
WE
t AS (1,4)
tO H Z
DOUT
t DW t DH
DIN
WRITE CYCLE 2
( OE = V
IL
Fixed)
tW C
A d d re s s
tC W tW R
CS
tA W tW P
WE
tA S tW H Z (1 ,4 ) tO W
tO H
(2 )
(3 )
DOUT
tD W tD H
D IN
DON'T CARE UNDEF INED
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 6
Publication Date: NOV. 2003 Revision: F
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T14L256A
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from D OUT are the same as the data written to D IN during the write cycle. 3. D OUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with C L = 5pF. guaranteed but not 100% tested. This parameter is
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 7
Publication Date: NOV. 2003 Revision: F
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T14L256A
PACKAGE DIMENSIONS 28-LEAD SOJ SRAM (300 mil)
SYMBOL A B C D E F G H I J K L M N O P Q y
DIMENSIONS IN INCHES 0.7100.002 0.3000.005 0.0600.002 0.0500.001 0.0630.001 0.0150.002 0.0300.002 0.0500.002 0.0180.002 0.0280.002 0.3370.002 0.0100.001 0.0260.002 0.2680.003 0.3000.002 0.0530.001 0.1400.004 0.004(MAX)
DIMENSIONS IN MM 18.030.05 7.620.13 1.520.05 1.270.03 1.630.03 0.380.05 0.760.05 1.270.05 0.460.05 0.710.05 8.560.05 0.250.03 0.660.05 6.810.08 7.620.05 1.350.03 3.560.10 0.10(MAX)
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 8
Publication Date: NOV. 2003 Revision: F
tm
1
TE CH
T14L256A
PACKAGE DIMENSIONS 28-LEAD TSOP-I SRAM (8X13.4mm)
D C 28 b E e 14 15 A2 "A" A A1 Seating plane y
Db Gauge plane Seating plane L
0.010
Detail "A"
L1
SYMBOL A A1 A2 b c Db E e D L L1 y
DIMENSIONS IN INCHES 0.047(max.) 0.0040.002 0.0390.002 0.008(typ.) 0.006(typ.) 0.4650.004 0.3150.004 0.022(typ.) 0.5280.008 0.0200.004 0.03150.004 0.004(max.) 0~5
DIMENSIONS IN MM 1.20(max.) 0.100.05 1.000.05 0.20(typ.) 0.15(typ.) 11.800.10 8.000.10 0.55(typ.) 13.400.20 0.500.10 0.800.10 0.10(max.) 0~5
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 9
Publication Date: NOV. 2003 Revision: F

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